RAM port connection
RAM port connection
I noticed that the port `adr` for the RAM module is 18bits, whilst it's driving signal RISC5.v is 24bits. I was hoping you could tell me how that's resolved during synthesis? Are only the 18LSB used?
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cfbsoftware
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Re: RAM port connection
Yes - that is my understanding. Vivado issues the warning:
If you prefer you can modify the adr parameter in the RAM statement in RISC5Top.v to match the address width actually used in the RAM module for your particular development board. e.g. in your case you should change it to
width (24) of port connection 'adr' does not match port width (18) of module 'RAM'
If you prefer you can modify the adr parameter in the RAM statement in RISC5Top.v to match the address width actually used in the RAM module for your particular development board. e.g. in your case you should change it to
Code: Select all
.adr(adr[0:17])