Astrobe Forum

Posted: **Thu Nov 16, 2023 12:26 pm**

For the Cortex-M0, the prologue and epilogue generated for interrupt handlers is the same as for normal parameterless procedures. That is, they are the same for

Code: Select all

PROCEDURE p0;
END p0;
0B500H          push     { lr }
046C0H          nop
0BD00H          pop      { pc }
046C0H          nop

and

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PROCEDURE p1[0];
END p1;
0B500H          push     { lr }
046C0H          nop
0BD00H          pop      { pc }
046C0H          nop

For the Cortex-M3, the interrupt handlers have entry and exit code to save and restore the registers that are not stacked by the MCU hardware.

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PROCEDURE p3[0];
END p3;
0E92D4FF0H      push.w   { r4, r5, r6, r7, r8, r9, r10, r11, lr }
0E8BD8FF0H      pop.w    { r4, r5, r6, r7, r8, r9, r10, r11, pc }

In my understanding, this means that on the M0 the registers R4 to R7 (R8 to R11 are not allocated by the compiler) are not "interrupt safe". Of course I can safe and restore these registers on source code level.

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PROCEDURE p1[0];
  VAR r4, r5, r6, r7: INTEGER;
BEGIN
  r4 := SYSTEM.REG(4);
  r5 := SYSTEM.REG(5);
  r6 := SYSTEM.REG(6);
  r7 := SYSTEM.REG(7);
  (* ... *)
  SYSTEM.LDREG(4, r4);
  SYSTEM.LDREG(5, r5);
  SYSTEM.LDREG(6, r6);
  SYSTEM.LDREG(7, r7)
END p1;
0B500H          push     { lr }
0B084H          sub      sp,#16

09400H          str      r4,[sp]
09501H          str      r5,[sp,#4]
09602H          str      r6,[sp,#8]
09703H          str      r7,[sp,#12]
    (* ... *)
09800H          ldr      r0,[sp]
04604H          mov      r4,r0
09801H          ldr      r0,[sp,#4]
04605H          mov      r5,r0
09802H          ldr      r0,[sp,#8]
04606H          mov      r6,r0
09803H          ldr      r0,[sp,#12]
04607H          mov      r7,r0

0B004H          add      sp,#16
046C0H          nop
0BD00H          pop      { pc }
046C0H          nop

Is this an intentional design decision? Or am I missing something here?

Posted: **Fri Nov 17, 2023 4:56 am**

Good question! Actually Cortex-M0 is OK but Cortex-M3 could be optimised.

Try adding some code to your Cortex-M0 interrupt handlers. You should see some or all of registers r4 - r7 saved if they are allocated by the compiler in the handler. Additionally, all registers r4-r7 are saved if another procedure is called by the handler.

If however, you use calls like LDREG in your handler to explicitly modify registers then you do need to save / restore them yourself.

Posted: **Fri Nov 17, 2023 9:54 am**

Wow. Smart. I am impressed. Thanks for that.

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