push {}
Posted: Tue May 14, 2019 10:19 am
I am dabbling with getting a stack trace upon run-time errors. For this, I obviously need to understand the structure of the stack when entering the error handler (SVC call).
A related questions about interrupt handlers in general.
I scoured the ARM docs, but didn't find any info on the 'push {}' instruction there in the prologue, ie. with an empty register list.
From the 'pop' instruction in the epilogue, I infer that this must do 'push { r4 r5 r6 r7 r8 r9 r10 r11 fp lr }', ie. the registers not pushed by the processor itself during the stacking phase of the exeception entry. (The processor will itself pop the other registers it has pused upon exit from the exception handler).
My stack trace works (but only indicating the module names and addresses, as I don't have the information about the procedures corresponding to the addresses), so I think my view of the stack structure, and how it is being built upon exception entry, is not far off. But I'd like to be sure.
Can you please enlighten me what 'push {}' means and does?
A related questions about interrupt handlers in general.
Code: Select all
PROCEDURE runtimeErrorHandler[0];
BEGIN
. 632 E92D0000H push { }
. 636 EA4F0C0DH mov fp,sp
(* ... *)
. 796 EA4F0D0CH mov sp,fp
. 800 E8BD9FF0H pop { r4 r5 r6 r7 r8 r9 r10 r11 fp pc }
From the 'pop' instruction in the epilogue, I infer that this must do 'push { r4 r5 r6 r7 r8 r9 r10 r11 fp lr }', ie. the registers not pushed by the processor itself during the stacking phase of the exeception entry. (The processor will itself pop the other registers it has pused upon exit from the exception handler).
My stack trace works (but only indicating the module names and addresses, as I don't have the information about the procedures corresponding to the addresses), so I think my view of the stack structure, and how it is being built upon exception entry, is not far off. But I'd like to be sure.
Can you please enlighten me what 'push {}' means and does?