Astrobe Forum

I'm trying to map the Project Oberon Workstation on the Nexys4 Rev B with the provided XDC file by email to me by you.
After generating the MCS file, configuring the QSPI FlashROM on the board, and burning 4GB micro SD card with the image provided, connecting keyboard and VGA monitor, putting Jumper on QSPI, pushing Prog button, I get a blank screen, and could be inverted by switch 3 on board; but Oberon is not booting.
Result by now: Blank video on VGA monitor, inverted video with switch 3 on board Nexys4 Rev B.

(To minimise any confusion I've created this new topic and moved the original message from the Arty A7-100 topic.)

We do not have the older Nexys 4 Rev B board so we are unable to test Project Oberon Workstation on it. However, it appears to similar enough to the Nexys A7-100T (which we are able to support properly) so we will do what we can to assist prospective users who have the older board and want to try porting Project Oberon Workstation to it.

The system is designed to display the boot progress via the diagnostic LEDs on the board. Look at the final display to see how far the system progressed in the boot process. That should help you to diagnose what the problem is. There was a useful message posted on the ETH Oberon Mailing list last year which documents which system states are indicated by the various combinations of the LEDs:

http://lists.inf.ethz.ch/pipermail/oberon/2020/015061.html

No LED is on, or blink or nothing. The only LEDs on are DONE and just an instant BUSY after PROG is pushed. After CPU_RST pressed, there is no change. I'm baffled.
On the same board I could start Embedded Oberon without problem but not PO WS.

Solved!
The problem is solved by adding and mapping prom.mem correctly in Vivado, in a parent directory as showed in PROM.v with: initial $readmemh("../prom.mem", mem);
I tried to relocate several times, but Vivado always failed to find the file, despite modifying the path in the Verilog readmemh function.

Great! I'm pleased to hear that you have got it working. I'll add a note to the installation instructions to point out that the folder structure should be maintained when unzipping the Verilog files.

We deliberately use the same folder structure as the official Project Oberon release. Is that why you are having problems getting the older official Spartan3 Project Oberon Workstation version working as reported on the ETH Oberon Mailing List?

I don't know right now, I need to retest the generation of the bitstream.
But as long as I remember I configured FPGA once and showed to students many times until one day (after a couple of years) it fails like I mention with a gray pattern on screen. Then I certainly tried to reconfigure and reburn image on SD card, and check connections on daughter board, etc.
Maybe I caused the same issue that I've been doing to Nexys4 version; I'll check it in a few days, because in this case I don't have a JTAG-USB programmer nor an old PC to use the parallel port to configure the old Spartan board by JTAG only method.
I'll try to build a JTAG programmer around an STM bluepill board as I briefly see elsewhere on the net.
Thank you for your thorough help.

This story has a happy ending as reported by Pablo on the ETH Oberon mailing list

http://lists.inf.ethz.ch/pipermail/oberon/2021/015888.html