Mapping to Nexys4 Cell RAM board

[pcayuela]

For Astrobe v7.2 for RISC5 I've been trying this XDC configuration, attached.
I did not have success communicating to Astrobe after configuring the FPGA in the board.
I need some help also to generate the ROM file; I'm only trying by USB JTAG with PROG UART connector.

[cfbsoftware]

Make sure that you are only using the files supplied for Embedded Project Oberon if you are using the constraints file you attached here. These files must not be mixed with the files supplied for Project Oberon Workstation.

The Embedded Project Oberon BootLoader ROM file is called prom.mem. You should not need to regenerate it.

The general steps required to configure the FPGA using Vivado Design Suite to run Embedded Project Oberon are as follows. Refer to Digilent's Vivado documentation for more details of each step.

1. Create a project (XPR) file which includes your modified constraints (XDC) file, the Embedded Project Oberon Verilog files and prom.mem. XPR and prom.mem are in the project folder, XDC and the Verilog files are in an 'src' subfolder.

2. Run the Generate Bitstream command. This will take about 10 minutes or so to complete.

3. Connect the Nexys 4 to your PC, Select Open Hardware Manager, Open Target and Auto Connect

4. Select Tools > Generate Memory Configuration File

5. Right-mouse button click on the name of your SPI flash device (e.g. s25fl128sxxxxxx0-spi) and select Program Configuration Memory Device. This should take a minute or two.

6. Close the Hardware Manager.

7. Power down the Nexys 4 and power it up again.

8. You should now be able to communicate with your board via the COM port that Windows has assigned to your USB connection to the board.

[pcayuela]

Thank you for your guide and advises. I have Embedded Oberon already running in the Nexys4 Cell RAM board.
Just for the sake of completeness:
Between the step 4 and 5 there are more ministeps not evident for me:
4.1 Choose Format: MCS
4.2 Choose Memory Part: s25fl128sxxxxxx0-spi
4.3 Choose a Filename: e.g. RISC5newflash.mcs
4.4 In the Options, choose Interface: SPIx4
4.5 Choose Load bitstream files, Start address: 00000000 Direction: up Bitfile: The bitstream generated file of .bit extension, e.g. RISC5Top.bit

The equivalent line command is this:
write_cfgmem -format mcs -size 16 -interface SPIx4 -loadbit {up 0x00000000 "E:/OberonGral/AstrobeRISC5viv/AstrobeRISC5viv.runs/impl_1/RISC5Top.bit" } -file "E:/OberonGral/AstrobeRISC5viv/RISC5newflash.mcs"

Then Step 5, etc.

Thank you again.
Prof Pablo Cayuela
Argentina

[cfbsoftware]

Thank you for the additional information. We used to supply the MCS files with the bitstream file but discovered that not only are these different for different boards, but also between different revisions of the same board

Anbody else reading this should note the following:

• You need to refer to the Digilent documentation for the specific revision of the board that you are using to determine exactly which Memory Part it is using.
• The type of Interface (e.g. SPIx4) depends on what is specified in the constraints (XDC) file that you are using.
• The folder locations will depend on how you have set up your own system.