Astrobe Forum

Regarding the very cool RISC5 Embedded Project Oberon, I wondered whether you've managed to make any further progress on the Cmod-a7-35T version?

Specifically, some progress in 1) access to the (512K) SRAM on the Cmod-a7-35T as with the original Project Oberon and Magnus' Pepino boards ? (From the Docs/Forum I understand Embedded Oberon RISC5 code runs only inside 192K BRAM of the FPGA right now). I looked and see the SRAM is mentioned in the Verilog Config file - but not yet hooked up, I think...

and 2) in adding I2C, maybe as you did with Magnus for Pepino with an I2C controller or even via bit-banging?

The 512K SRAM on the Cmod A7-35T only has 8-bit wide access which limits its performance in a 32-bit system like RISC5 Oberon. If you want I2C Master capabilities and access to more RAM (i.e. 480 KBytes) in a RISC5 system I recommend that you try the Digilent Arty A7 or Nexys A7 boards which use the Artix 7-100T FPGA.